The present invention relates generally to semiconductor device processing techniques and, more particularly, to a method for adjusting lithographic mask flatness using thermally-induced pellicle stress.
Semiconductor fabrication techniques often utilize a mask or reticle in a conventional lithographic system to project an image onto a semiconductor wafer, wherein radiation is provided through (or reflected off) the mask or reticle, and passed through a focusing optical system to form the image (e.g., an integrated circuit pattern). The semiconductor wafer is positioned to receive the radiation transmitted through (or reflected off) the mask such that the image formed on the wafer corresponds to the pattern on the mask. The radiation source may be light, such as ultraviolet light, vacuum ultraviolet (VUV) light, extreme ultraviolet light (EUV) and deep ultraviolet light (DUV). In addition, the radiation may also be x-ray radiation, e-beam radiation, etc. Generally, the formed image is utilized on the wafer to pattern a layer of material, such as a photoresist material. The photoresist material, in turn, may be utilized to define doping regions, deposition regions, etching regions, or other structures associated with the manufacture of integrated circuits (ICs).
Reticle flatness has become increasingly important as lithographic focus windows shrink. A smaller process window is undesirable for semiconductor manufacturing where process drifts could shift the operating point away from the optimal dose and/or focus range. The smaller the process window, the more likely yield loss will occur when the process drifts. Mask non-flatness consumes some of the process window; for example, a typical specification for mask blank flatness is less than 2 microns. At this maximum allowable value, the resulting impact is about 175 nanometers (nm) at the wafer. However, this value is on the order of the entire focus budget for some critical mask levels. On the other hand, a reticle flatness of 0.5 microns or better corresponds to less than 30 nm impact at the wafer, which is more tolerable.
It is undesirable to rely solely on incoming substrate flatness to meet desired tolerances. Flatter masks are more expensive to order, and because they push technology limits, they are not always within the tight specification limits. Moreover, both mask processing and pellicle mounting processes contribute to adverse changes in flatness. A pellicle is a thin, optically-transparent membrane used to protect patterned photomask surfaces from contamination by airborne particles. Typically, the pellicle includes a metal (e.g., aluminum) frame having one or more of the walls thereof securely attached to a chrome side of the mask or reticle. The membrane is stretched across the metal frame and prevents the contaminants from reaching the mask or reticle. Since the particles that fall on the pellicle are out of focus, they do not distort the image printed on the wafer.
Unfortunately, the mounting of the pellicle frame can alter mask flatness by exerting mechanical stresses on the mask. For example, recent technical articles have described how pellicles can affect the shape of the mask as a function of initial pellicle flatness and temperature change (Cotte et al., Experimental and Numerical studies of the Effects of Materials and Attachment Conditions on Pellicle-Induced Distortions in Advanced Photomasks, SPIE Vol. 4754, pp. 579-588 (2002)).
Accordingly, it would be desirable to implement a pellicle mounting process wherein reticle flatness is not adversely affected and, even more advantageously, wherein existing reticle flatness may be improved following pellicle attachment.